5月8日-10日，由EDA开放创新合作机制（EDA²）主办，IEEE/CEDA、ACM/SIGDA作为顾问单位，新加坡半导体协会、Siliconexus协办的2026年International Symposium of EDA（ISEDA 2026）在新加坡顺利召开。会议设置11场大会报告、7场培训班、3场研讨会、2场特别分会、21场技术分论坛及1场海报展示论坛等，吸引来自10个国家和地区的400余名专家学者齐聚狮城，共探EDA领域创新发展。
北京大学集成电路学院师生代表积极参与大会组织筹办、专题报告、技术论坛及海报展示等环节。王润声教授担任大会General Chair，梁云教授担任Keynote Chair，林亦波教授担任Physical Implementation Track Committee Chair，李萌教授担任Design for Manufacturability and Reliability Track Committee Chair，林亦波、李萌、贾天宇等同时也担任大会相关环节主席。本届大会中，北京大学共有5篇论文入选最佳论文提名，其中1篇论文获最佳论文奖。
ISEDA 2026会议现场合影
部分参会师生和校友合影
5月8日，会议正式开幕。GlobalFoundries、ISEDA 2026大会主席Hui, Chiu Wing Colin致欢迎辞，对来到新加坡的全球专家学者表示热烈欢迎。Colin介绍了大会整体安排与亮点，并祝愿与会者在学术交流中收获前沿启发，也在新加坡感受多元文化与创新活力。
Hui, Chiu Wing Colin致欢迎辞
香港中文大学余备教授在技术委员会报告中介绍，ISEDA持续搭建覆盖器件、芯片、系统及应用的高水平学术交流平台。本次ISEDA 2026投稿数量再创新高，共录用来自11个国家和地区的200余篇高质量论文，覆盖12大征稿主题，并持续以最佳论文奖鼓励原创研究与高质量学术报告。
余备教授作技术委员会报告
开幕式上，“AI for EDA & Cross Level Synthesis技术路线图”发布仪式同步启动，展示了AI与芯片设计深度融合的前沿方向。
“AI for EDA & Cross Level Synthesis技术路线图”发布仪式
EDA²理事长、北京大学王润声教授正式宣布ISEDA 2027将于2027年5月在北京举办，届时诚邀全球EDA同仁明年相聚北京，共同见证多元化EDA的发展。
王润声教授宣布ISEDA 2027将在北京举办
大会报告环节邀请到来自世界各地的11位专家：博洛尼亚大学Benini, Luca教授，A*STAR行政副总裁Yeo, Yee Chia教授，Applied Materials副总裁兼总经理Kengeri, Subramani，新加坡科技设计大学Yeo, Kiat Seng教授，Cadence Design Systems副总裁Chan, Don，明尼苏达大学Parhi, Keshab教授，亚利桑那州立大学Chakrabarty, Krishnendu教授，新加坡国立大学Alioto, Massimo教授，东京科学大学Takahashi, Atsushi教授，斯图加特大学Wunderlich, Hans-Joachim教授，加州大学洛杉矶分校Gupta, Puneet教授。专家们围绕先进制程设计、智能化EDA工具、芯片-系统协同优化等议题，分享EDA领域的标志性成果与未来趋势。
晚宴上，颁发了ISEDA 2026最佳论文奖，来自东南大学的《KAN-CHAR: Efficient Cell Library Characterization for DTCO via Kolmogorov-Arnold Graph Learning》和来自北京大学的《DTCO Dual-Sided Standard Cells with DP-Based Optimization and Custom Library Development》两篇论文获奖。
5月8日至10日，会议围绕EDA与集成电路设计领域的核心议题，组织专题研讨会（Panels）、特别分会（Special Sessions）、研讨会（Workshop）、培训班（Tutorials）、技术分会（Technical Sessions）以及海报展示（Poster Session）等多类学术活动，覆盖从基础方法到前沿探索的多个维度。Synopsys、Cadence和Siemens EDA三大国际厂商也在Keynote、Invited Talk、Panel等环节亮相，为本届大会带来更多产业视角。
本次大会收录的我校师生论文情况如下：
[1] Fengyuan Guo, Hongxiao Zhao, Jiayi Li, Anjunyi Fan, Yihan Fu, Wenshuo Yue, Bonan Yan, “CoPU-RL: A Hardware-Friendly Training-Inference Framework For Neuro-Symbolic Reinforcement Learning”（最佳论文候选）.
[2] Haoran Li, Yukun Wang, Hu Zhou, Guangyu Sun, Guojie Luo, “Sparse-GCS: A High-Performance GPU Timer for Composite Current Source Model-Based STA”.
[3] Haichuan Liu, Zizheng Guo, Runsheng Wang, Yibo Lin, “ElmoreCeff: A GPU-Friendly Elmore-Like Delay Calculator with a Closed-Form Effective Capacitance Model”.
[4] Xun Jiang, Haoran Lu, Yifan Chen, Yibo Zhang, Jianxiang Jin, Jiarui Wang, Chunyuan Zhao, Heng Wu, Runsheng Wang, Yibo Lin, “Flexible Double-Side Pin Redistribution with Efficient Virtual-Net-Guided Cell Type Assignment”（最佳论文候选）.
[5] Yuxiang Zhou, Yu Li, Guibo Luo, Runsheng Wang, Lining Zhang, “AgenticPE: A Dual-Agent LLM Framework with Physics-Gated Reasoning and Trajectory-Aware Optimization for Model Parameter Extraction”.
[6] Yukun Li, Jiajun Qiu, Sannian Song, Lining Zhang, “A Physics-Based OTS Compact Model with Force-Driven Adaptive Damping and Differentiable Hysteresis”.
[7] Jincheng Lou, Ruohan Xu, Jiecheng Ma, Runzhe Tao, Xinyu Qu, Yibo Lin, “LEGO: An LLM Skill-Based Front-End Design Generation Platform”（最佳论文候选）.
[8] Xiao Tan, Chenyue Li, Sunan Zou, Wei Yan, Guojie Luo, “RTLPilot: Skill-Driven Multi-Agent System for RTL Code Migration”.
[9] Zizhuo Fu, Yifan Zhou, Zhaoxin Lu, Guangyu Sun, Runsheng Wang, Meng Li, Yibo Lin, “RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System”.
[10] Jinghan Xu, Zheng Zhou, Yongjia Wang, Shuhan Wang, Ligong Zhang, Xiaoyan Liu, “Reliability-aware DTCO with Physics-Constrained Machine Learning Framework for MOSFETs Trap Extraction”.
[11] Qincheng Yang, Xianyu Wang, Jiajun Qiu, Guangyu Sun, Runsheng Wang, Lining Zhang, “H-COSY: Hardware-Calibrated Co-Optimization for Device-Circuit Synergy in Ferroelectric SNNs”.
[12] Boyi Fu, Weikai Xu, Tong Xie, Jin Luo, Yaoyu Tao, Meng Li, “NICE: 3D-NAND-based In-Memory-Computing with In-Situ ECC-Protection for Fault-Tolerant and Efficient LLM Inference”.
[13] Sihao Chen, Baicheng Lin, Jie Lin, Yushen Zhang, Ulf Schlichtmann, Lining Zhang, Runsheng Wang, “Parasitic-aware SRAM Designs with 2nm Predictive Technology Incorporating Backside Contact”.
[14] Jinwei Zhou, Xiping Dong, Yi Ren, Chenhao Xue, Jiaxing Zhang, Yihan Yin, Guangyu Sun, Xinnan Lin, “MFchip: A Multi-FPGA Emulation Platform for Chiplet-Based Systems with Latency and Bandwidth Adaptation”.
[15] Yuxiang Zhao, Jing Mai, Zishu Li, Haoyi Zhang, Jincheng Lou, Qing He, Runsheng Wang, Yibo Lin, “PowerCube: A Formula-in-the-Loop Framework for Cross-Stage Power Map Prediction”.
[16] Tong Xie, Zuodong Zhang, Chao Yang, Yuan Wang, Runsheng Wang, Meng Li, “Aging Aware Adaptive Voltage Scaling for Reliable and Efficient AI Accelerators”.
[17] Xizhe Shi, Zizheng Guo, Yun Liang, Runsheng Wang, Yibo Lin, “HeteroPower: A CPU-GPU Heterogeneous Engine to Accelerate Gate-Level Power Analysis”（最佳论文候选）.
[18] Kairong Guo, Jiechen Huang, Wenjian Yu, Yibo Lin, “CAPCell: Standard Cell Layout Synthesis with Parasitic Capacitance Aware Parallel Sampling”.
[19] Qinzhe Zhi, Peijie Ma, Heng Wu, Tianyu Jia, “DTCO Dual-Sided Standard Cells with DP-Based Optimization and Custom Library Development”（最佳论文）.
[20] Bingyang Liu, Haoning Jiang, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, David Z. Pan, Yibo Lin, “GRAIN: A Design-Intent-Driven Analog Layout Migration Framework”.
[21] Xiping Dong, Yihan Yin, Guangyu Sun, “HiMoE-NoC: A Hierarchical Network-on-Chip Design Framework for MoE Inference on 3D-Stacked DRAM Accelerators”.
[22] Yujie Li, Xiaole Cui, Juncheng Pu, “A Fault Diagnosis Method of SerDes Circuit”.
（根据EDA2等相关新闻编辑）
