1.Tianyu Jia et al., A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP Blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC, IEEE 48th European Solid-State Circuits Conference (ESSCIRC), Sep. 2022.
2.Tianyu Jia et al., NCPU: An embedded neural CPU architecture on resource-constrained low power devices for real-time end-to-end performance, International Symposium on Microarchitecture (MICRO), Oct. 2020.
3.Tianyu Jia et al., A compute-adaptive elastic clock chain technique with dynamic timing enhancement for 2D PE array based accelerators, International Solid-State Circuits Conference (ISSCC), Feb. 2020.
4.Tianyu Jia et al., An adaptive clock scheme exploiting instruction-based dynamic timing slack for a GPGPU architecture, IEEE Journal of Solid-State Circuits (JSSC), 2020.
5.Tianyu Jia et al., A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique, IEEE Journal of Solid-State Circuits (JSSC), 2020.
6.Tianyu Jia et al., An adaptive clock management scheme exploiting instruction-based dynamic timing slack for general-purpose graphic processor unit with deep pipeline and out-of-order execution, International Solid-State Circuits Conference (ISSCC), Feb. 2019.
