在代表集成电路设计最高水平的“芯片奥林匹克大会”ISSCC发表论文6篇。2018年发表北京大学在ISSCC的首篇论文，获2022年度国际固态电路会议ISSCC Highlight亮点论文2次。申请专利40多项，其中授权美国发明专利12项。在高速通信芯片领域的研究居国际领先水平，包揽我国大陆在Wireline收发机领域的所有ISSCC论文。部分研究成果已在国内外多家头部企业获得产业化应用。
代表性论文
K. Sheng, H. Niu, B. Zhang, W. Gai, B. Ye, H. Zhou, and C. Chen, “A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS,” 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.282-283.
B. Ye, K. Sheng, W. Gai, H. Niu, B. Zhang, Y. He, S. Jia, C. Chen, and J. Yu, “A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.118-119.
L. Tang, W. Gai, L. Shi, X. Xiang, K. Sheng, and A. He, “A 32Gb/s 133mW PAM-4 Transceiver with DFE Based on Adaptive Clock Phase and Threshold Voltage in 65nm CMOS,” 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2018, pp. 114-116.
Y. Hidaka, W. Gai, T. Horie, J. H. Jiang, Y. Koyanagi, and H. Osone, “A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro with 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” in IEEE Journal of Solid-State Circuits (JSSC), Vol. 44, No. 12, pp.3547-59, Dec. 2009.
Y. Hidaka, W. Gai, T. Horie, J. H. Jiang, Y. Koyanagi, and H. Osone, “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” 2009 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.188-189.
Y. Hidaka, W. Gai, A. Hattori, T. Horie, J. Jiang, K. Kanda, Y. Koyanagi, S. Matsubara, and H. Osone, “A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer,” 2007 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.442-443.
Y. Hidaka, W. Gai, H. Osone, Y. Koyanagi, J. H. Jiang, and T. Horie, “Gain-Phase Co-Equalization for Widely-Used High-Speed Cables,” 2005 Symposium on VLSI Circuits (VLSIC), Kyoto, Japan, 2005, pp.194-197.
W. Gai, Y. Hidaka, Y. Koyanagi, J. H. Jiang, H. Osone, and T. Horie, “A 4-Channel 3.125Gb/s/ch CMOS Transceiver with 30dB Equalization,” 2004 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 2004, pp.138-141.
K. Gotoh, H. Tamura, H. Takauchi, T. S. Cheung, W. Gai, Y. Koyanagi, R. Schober, R. Sastry, and F. Chen, “A 2B Parallel 1.25 Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking,” 1999 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.180-181.
