在代表集成电路设计最高水平的“芯片奥林匹克大会”ISSCC和顶级期刊IEEE JSSC发表论文12篇。2018年发表北京大学在ISSCC的首篇论文，获2022年度国际固态电路会议ISSCC Highlight亮点论文2次。申请专利40多项，其中授权美国发明专利12项。在高速通信芯片领域的研究居国际领先水平，包揽我国大陆在Wireline收发机领域的所有ISSCC论文。部分研究成果已在国内外多家头部企业获得产业化应用。
代表性论文
[1] “A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS,” 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 112-113
[2] “A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS,” 2023 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2023, pp. 120-121
[3] “A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS,” in IEEE Journal of Solid-State Circuits (JSSC), Vol. 58, No. 1, pp. 45-56, Jan. 2023
[4] “A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS,” in IEEE Journal of Solid-State Circuits (JSSC), Vol. 58, No. 1, pp. 19-29, Jan. 2023
[5] “A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS,” 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.282-283
[6] “A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.118-119
[7] “A 32Gb/s 133mW PAM-4 Transceiver with DFE Based on Adaptive Clock Phase and Threshold Voltage in 65nm CMOS,” 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2018, pp. 114-116
[8] “A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro with 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” in IEEE Journal of Solid-State Circuits (JSSC), Vol. 44, No. 12, pp.3547-59, Dec. 2009
[9] “A 4-Channel 10.3Gb/s Backplane Transceiver Macro with 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” 2009 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.188-189
[10] “A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer,” 2007 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.442-443
